1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device provided with a microelectronic storage capacitor for storing a charge to represent information or data therein, in which capacitor a tantalum oxide (i.e., Ta.sub.2 O.sub.5) film is used as a capacitance insulation film.
2. Description of the Related Art
In general, LSI (i.e., Large Scale Integration) circuits, which typify semiconductor devices, are classified into two categories, i.e., memory products and logic products. In recent years, particularly, the former (i.e., memory products) have been making a remarkable progress along with recent developments in semiconductor fabrication techniques. Further, the memory products are classified into two subcategories, i.e., DRAMs (i.e., Dynamic Random Access Memories) and SRAMs (i.e., Static Random Access Memories). Most of these memory products are constructed of the MOS (i.e., Metal Oxide Semiconductor) transistors excellent in integration density. In comparison with the SRAMs, since the DRAMs are capable of more effectively using their advantages in integration density, it is possible for the DRAMs to realize the cost reduction in manufacturing, which enhances their application to various memory units in information instruments and like equipment or systems.
In operation, since the DRAMs store charges representing data or information in their microelectronic capacitors, the individual microelectronic capacitors formed in the semiconductor substrates of the DRAMs are restricted in their occupation areas as the volume of information being stored in the DRAMs increases. Consequently, a need exists in the art for an improved technique that increases the microelectronic capacitors of the DRAMs in capacitance (i.e., electrostatic capacity). When these capacitors of the DRAMs are not sufficient in capacitance for storing charges representing the data or information, the DRAMs often fail to function properly under the influence of external noise signals and the like, which causes various types of errors, for example, typified by errors in operation various software programs and the like.
Heretofore, a silicon oxynitride (i.e., SiON) film, which is reduced in film thickness and serves as a capacitance insulation film of the microelectronic capacitor, has been obtained by nitrifying a silicon oxide (i.e., SiO.sub.2) film. However, in such a silicon oxynitride film thus obtained, its minimum allowable film thickness when expressed in oxide-film converted film thickness (i.e., equivalent oxide thickness) Teff is within a range of from 45 to 50 Angstroms, which is a critical point of occurrence of a tunnel current of the transistor, wherein: Teff is a capacitance per unit area of the thus formed capacitor. In order to increase the capacitor in capacitance, heretofore, various types of three-dimensional configurations of electrodes, for example such as those of box types, cylinder types, fin types, HSG (i.e., Hemispherical Grain) types, and of like types have been proposed to increase the capacitor's electrode in surface area. Although much more complicated configurations have been proposed with respect to the capacitor's electrode in the art of today, since there is a severe restriction in space in the transistor, it is hard to increase the capacitor in capacitance by increasing the surface area of the capacitor's electrode. Due to the existence of the above difficulty, widely used in the art of today in order to increase the capacitor in capacitance is a technique that utilizes a high-dielectric-constant material in the capacitance insulation film of the capacitor.
In the art of today, there are known various types of the high-dielectric-constant materials. However, in case that these materials are employed in the capacitance insulation films of the capacitors, it is necessary to previously check them in terms of: easiness in forming them into a film; and, compatibility with a pair of the electrodes disposed adjacent to opposite surfaces of the capacitance insulation film made of these materials. Consequently, a dielectric material, even when it is sufficiently high in dielectric constant, is not necessarily employed as a material for the capacitance insulation film of the capacitor. Under such circumstances, widely used in the art as a material for the capacitance insulation film of the capacitor is tantalum oxide. The dielectric constant (a value of which is within a range of from 40 to 47) of a film made of tantalum oxide (hereinafter referred to as the tantalum oxide film) is ten times higher than the dielectric constant of a silicon oxide film having been heretofore used as the capacitance insulation film in the art, and is six times higher than the dielectric constant of a silicon nitride film (i.e., Si.sub.3 N.sub.4). Further, the tantalum oxide film is easier in formation. Consequently, it is possible to increase the capacitor in capacitance by using the tantalum oxide film as the capacitance insulation film in the capacitor.
FIGS. 14A to 14C show a conventional method for manufacturing a semiconductor device. Now, with reference to these drawings, the conventional method for manufacturing the semiconductor device will be described according to its process step.
First, as shown in FIG. 14A, for example, according to conventional known techniques, a P-type semiconductor substrate 51 is prepared. Then, formed in a surface of this semiconductor substrate 51 are: an N-type source region 52 and an N-type drain region 53 which is spaced apart from the source region 52; a gate insulation film 54 formed on the surface of the substrate 51 between the source region 52 and the drain region 53; and, a gate electrode 55 formed on the gate insulation film 54, so that an N-type MOS transistor 56 is formed on the semiconductor substrate 51. The thus formed N-type MOS transistor 56 is combined with a microelectronic capacitor 64 (shown in FIG. 14C) to form a single memory cell of the semiconductor device. In FIG. 14A: the reference numeral 57 denotes an interlayer insulation film which covers the entire upper surface of the semiconductor device; and, the reference numeral 58 denotes an element isolating insulation film for isolating the individual regions of the semiconductor device from each other.
Next, as shown in FIG. 14B, a minute contact hole 59 is formed in the interlayer insulation film 57 in a position corresponding to the N-type drain region 53 (or the N-type source region 52) of the N-type MOS transistor 56. After that, a conductive film is formed to cover the entire upper surface of the semiconductor device including the entire inner surface of the contact hole 59 so as to be electrically connected with the N-type drain region 53 (or the N-type source region 52). Then, the thus formed conductive film is patterned and formed into a lower electrode (i.e., storage electrode) 61 of the capacitor 64, as shown in FIG. 14B.
After completion of formation of the lower electrode 61 of the capacitor 64 (shown in FIG. 14C), a tantalum oxide film 62 is formed to have an appropriate film thickness by a CVD (i.e. Chemical Vapor Deposition) process to serve as a capacitance insulation film of the capacitor 64, as shown in FIG. 14C. In the CVD process, the semiconductor substrate 51 is received in a reactor container of a CVD apparatus. After that, in a condition in which the interior of the reactor container is kept at a predetermined steady film forming pressure, a mixture gas containing: pentaethoxy tantalum, i.e., one of tantalum alkoxides; and, oxygen is fed to the reactor container so that film forming processes are performed inside the reactor container, whereby the tantalum oxide film 62 having a desired film thickness is formed inside the reactor container. After that, an upper electrode (i.e., plate electrode) 63 is formed on the thus formed tantalum oxide film 62, which makes it possible for the tantalum oxide film 62 to serve as the capacitance insulation film of the capacitor 64. As shown in FIG. 14C, disposed adjacent to an upper and a lower surface of the tantalum oxide film 62 are the upper electrode 63 and the lower electrode 61, respectively, whereby the capacitor 64 is formed. As is described in the above, the capacitor 64 is electrically connected in series with the N-type MOS transistor 56 to form the memory cell of the semiconductor device.
On the other hand, as described above with reference to FIG. 14C, when the tantalum oxide film 62 is formed with the use of the organic source gas, the tantalum oxide film 62 thus formed contains a few percent of carbon. Consequently, when various types of heat treatments are performed later in a process for manufacturing the LSIs, carbon contained in the tantalum oxide film 62 combines with oxygen of the tantalum oxide film 62 to become CO or CO.sub.2 gas which escapes from the tantalum oxide film 62. Due to such escape of CO or CO.sub.2 gas from the tantalum oxide film 62, a concentration of oxygen in the tantalum oxide film 62 reduces, which facilitates current leakage through the tantalum oxide film 62 serving as the capacitance insulation film of the capacitor 64.
In order to prevent such current leakage from occurring in the tantalum oxide film 62 due to the lack of oxygen contained in the tantalum oxide film 62, for example, in a conventional method for manufacturing a semiconductor device disclosed in Japanese Patent Laid-Open No. Hei 9-121035, a microelectronic capacitor of the semiconductor device is fabricated in a manner such that: a tantalum oxide film is formed on a lower electrode of the semiconductor substrate in a first film forming step; in a second film forming step subsequent to the first film forming step, an ultraviolet ray-ozone annealing process (hereinafter referred to as the UV-O.sub.3 annealing process) is performed with respect to the semiconductor device provided with the tantalum oxide film thus formed therein; and, in a third film forming step subsequent to the second film forming step, the first and the second film forming step are repeatedly performed.
Although the conventional method disclosed in the Japanese Patent Laid-Open No. Hei 9-121035 is capable of preventing occurrence of the current leakage caused by the lack of oxygen contained in the tantalum oxide film serving as the capacitance insulation film of the capacitor, such conventional method suffers from deterioration in physical properties (i.e., film quality) of the tantalum oxide film.
In other words, according to experiments conducted by the inventor of the present invention, it has been found that: the conventional method produces a low-dielectric-constant film in the boundary of the lower electrode; and, it is very hard to modify or improve the thus formed low-dielectric-constant film in physical properties (i.e., film quality). Further, due to the existence of such low-dielectric-constant film, the tantalum oxide film of the semiconductor device fabricated by the conventional method is poor in TDDB (i.e., Time Dependent Dielectric Breakdown) characteristics. Consequently, also in this respect, the tantalum oxide film is poor in physical properties.
Further, in order to increase the capacitor of the semiconductor device in capacitance, it is necessary to reduce the film thickness of the tantalum oxide film to the smallest possible value for preventing occurrence of the current leakage in the tantalum oxide film. In order to meet such need, it is necessary to improve the tantalum oxide film (i.e., capacitance insulation film) both in film quality and in coverage. In other words, since the tantalum oxide film serving as the capacitance insulation film of the capacitor in the semiconductor device is formed on a so-called HSG (i.e., Hemispherical Grain) conductive silicon film which has been formed on the lower electrode and increased in its surface area with its rough surface, its coverage problem becomes critical.